The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs) realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode that is formed on a semiconductor substrate and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. The MOS transistor is accessed via conductive contacts formed on the source and drain regions.
Some ICs are formed using both P-channel FETs (PMOS transistors) and N-channel FETs (NMOS transistors), referred to as a complementary MOS or CMOS integrated circuit. Often, the IC will include transistors which interface with other electrical components outside the IC (i.e., the input/output (or I/O) transistors) as well as transistors that implement the internal logic functionality for the IC (i.e., the logic transistors). The I/O transistors typically operate at higher voltage levels than the logic transistors, and as a result, the I/O transistors often utilize a thick gate oxide. When the channel of the I/O transistor comprises material, such as silicon germanium (SiGe) or silicon carbide (SiC), the gate oxide may be formed by depositing an oxide to the desired thickness. Deposited oxide could be sub-stoichiometric and contain impurities and/or broken bonds. As a result, when an oxygen-gettering material is used in the gate-stack, oxygen from the deposited oxide is more likely to diffuse to the oxygen-gettering material during subsequent high temperature process steps. This results in non-uniform gate oxide thickness, increased gate leakage, degraded time-dependent dielectric breakdown (TDDB), and variation in threshold voltage for the I/O transistors.